Apparatus for recovering symbol timing in cap-based high-speed communication system using single-sided prefilter pair

Abstract

An apparatus for recovering symbol timing in a CAP-based high-speed communication system such as an ADSL or VDSL, using a single-sided prefilter pair, in which timing information is obtained by means of the single-sided prefilter pair and a multiplier instead of a squaring unit used in general communication systems, for the recovery of accurate data, so that the symbol timing can be recovered through a digital signal process at a clock rate which is four times as high as a symbol transmission rate. According to the present invention, the single-sided prefilter pair and multiplier are used instead of the squaring unit spreading a frequency band. Therefore, the frequency band is not spread, so that the timing can be obtained with no signal overlapping due to sampling, although a sampling frequency is four times as high as a symbol frequency. Further, band components unnecessary to the timing information extraction are removed from a transmitted signal by filtering it respectively at higher and lower frequency bands, and the timing information is obtained by multiplying the two filtered signals by each other. These have the effect of reducing a timing jitter which may occur on a specific pattern of data due to the filtering.