Intelligent error recovery flow prediction for low latency NAND flash memory저지연 NAND 플래시 메모리를 위한 지능형 에러복구 흐름 예측에 대한 연구

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The reliability issue of the NAND flash memory has been raised resulting from decreasing the physical distance between transistors and the gap of each symbol due to the multi-leveling technology and fine processing technology. To mitigate the increase in the error rate of the memory, error recovery techniques with high reliability are required. Low density parity check codes using soft decision information, and read retry techniques that move the read voltage closer to the intersection of the distribution are currently used. However, these error recovery techniques need high read latency, leading to consideration of the trade-off between reliability and read latency. As it is difficult for the controller to know about the current cell state, these error recovery techniques tend to be applied in a fixed and sequential order from low to high latency and error correction capability regardless of the current state of degradation. This results in high read latency to recover errors of data as the deterioration condition increases, which is a factor in shortening the lifespan of an SSD using NAND flash memory. In this paper, we propose a one- shot error recovery method based on supervised learning, that achieves both the minimum read latency and successful decoding by setting an optimal starting point for the current cell state. We consider the input features that don’t need any structural and latency overhead for the machine learning model. This enables our proposed scheme to set an optimal start point that makes a success of one-shot error recovery without additional latency. Also, we show that transfer learning can be implemented to fastly adapt to variational distributions due to process variations, which results in mitigating the degradation in the performance of the proposed scheme. Simulation results show that our proposed method can significantly improve the average read latency performance compared to conventional error recovery flows and reach the near optimal latency performance, through predicting the optimal starting point for one-shot error recovery with high accuracy.
Advisors
Park, Hyuncheolresearcher박현철researcher
Description
한국과학기술원 :전기및전자공학부,
Publisher
한국과학기술원
Issue Date
2021
Identifier
325007
Language
eng
Description

학위논문(석사) - 한국과학기술원 : 전기및전자공학부, 2021.2,[ⅳ, 38 p. :]

Keywords

NAND Flash Memory System▼aError Management▼aError Correction Codes▼aMachine Learning▼aDeep Learning▼aTransfer Learning▼aLatency Minimization; NAND 플래시 메모리 시스템▼a에러 관리▼a에러 정정 부호▼a머신 러닝▼a딥 러닝▼a전이 학습▼a저지연 메모리

URI
http://hdl.handle.net/10203/295993
Link
http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=948673&flag=dissertation
Appears in Collection
EE-Theses_Master(석사논문)
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