Supply noise insensitive clock distribution network for mobile DRAM

Abstract

Nowadays, internet data traffic is increasing with the development of information and communication technology. In recent years, mobile data traffic is increasing due to the increase in the use of mobile devices, and the performance of mobile devices for processing such a large amount of data is also steadily improving. The clock speed is steadily increasing to increase the data processing speed of mobile devices, and the power supply voltage is also lowered to increase the battery usage time. This trend is similarly seen in mobile application processors and graphics processors and in DRAM, which is one of the key components of mobile devices. In the case of mobile DRAM, LPDDR5, which can process data of 6.4Gb/s/pin, was recently announced, and on a single chip basis, it exceeds the data processing speed of DRAM for personal computers and servers. As the clock speed of the mobile DRAM increases and the power supply voltage decreases, the clock jitter due to power supply noise is increasing, and such clock jitter makes high-speed operation of the DRAM more difficult. The clock jitter of DRAM is mainly caused by power supply noise in the clock distribution network. In this thesis, a novel architecture of a clock distribution network for DRAM using an adaptive filter was proposed to compensate the clock jitter generated in the clock distribution network due to the power supply noise of the DRAM. The proposed clock distribution network is based on LPDDR5's clock distribution network and its operating voltage is 1.0V and its operating speed is 6.4Gb/s. In an environment where the power supply noise to 50mV$_{pp}$, the data-eye has increased from 45ps to 105ps, and the jitter of the clock has decreased from 21.7ps to 2.6ps.