Processing in-memory architecture for binary neural networks바이너리 신경망을 위한 메모리 내부 처리 아키텍처 연구

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Popular deep learning technologies suffer from memory bottlenecks, which significantly degrade the energy-efficiency, especially in mobile environments. Processing in-memory (PIM) for binary neural networks (BNNs) has emerged as a promising solution to mitigate such bottlenecks, and various relevant works have been presented accordingly. However, their performances are severely limited by the overheads induced by modifying the conventional memory architectures. To alleviate the performance degradation, this dissertation proposes NAND-Net, an efficient architecture to minimize the computational complexity of PIM architecture for BNNs. Based on the observation that BNNs contain many redundancies, each convolution is decomposed into sub-convolutions, and the unnecessary operations are eliminated. In the remaining convolution, each binary multiplication (bitwise XNOR) is replaced by a bitwise NAND operation, which can be implemented without any bit cell modifications. This NAND operation further brings an opportunity to simplify the subsequent binary accumulations (popcounts). The operation cost of those popcounts is reduced by exploiting the data patterns of the NAND outputs. Compared to the prior state-of-the-art designs, NAND-Net achieves 1.04-2.4x speedup and 34-59% energy saving. Meanwhile, the efficiency of the mixed-signal manner of PIM architecture is mostly compromised by the tremendous cost of domain conversion circuits such as analog-to-digital converters (ADCs). This dissertation identifies the root causes of the need for such ADCs and proposes novel solutions to address them. First, the BNN algorithm is decomposed and reconstructed to become perfectly suitable for the crossbar arrays in PIM. This recombination minimizes redundant operations in the BNN, reducing the number of crossbar arrays with ADCs to be accumulated by half. Moreover, the dynamic range of bit-line currents in each crossbar array is decreased by exploiting the inter-layer dependency of BNNs. Appropriately handling the partial-sum current distribution can make it possible to perform BNN processing without domain conversions, bypassing the need for ADCs completely. The experimental results show that our proposed architecture achieves 3.44x speedup and 91.5% energy saving, thereby visualizing the usability of the PIM architecture for BNNs in various applications.
Advisors
Kim, Lee Supresearcher김이섭researcher
Description
한국과학기술원 :전기및전자공학부,
Publisher
한국과학기술원
Issue Date
2021
Identifier
325007
Language
eng
Description

학위논문(박사) - 한국과학기술원 : 전기및전자공학부, 2021.8,[v, 56 p. :]

Keywords

Deep neural network▼aBinary neural network▼aProcessing in-memory▼aConvolution▼aPopcount▼aDomain conversion▼aADC▼aSRAM▼aDRAM▼aReRAM; 심층 신경망▼a바이너리 신경망▼a메모리 내부 처리▼a컨볼루션▼a팝카운트▼a도메인 변환▼a아날로그-디지털 변환회로▼aSRAM▼aDRAM▼aReRAM

URI
http://hdl.handle.net/10203/295619
Link
http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=962465&flag=dissertation
Appears in Collection
EE-Theses_Ph.D.(박사논문)
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