Power Reduction in Punch-Through Current-Based Electro-Thermal Annealing in Gate-All-Around FETs

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Device guidelines for reducing power with punch-through current annealing in gate-all-around (GAA) FETs were investigated based on three-dimensional (3D) simulations. We studied and compared how different geometric dimensions and materials of GAA FETs impact heat management when down-scaling. In order to maximize power efficiency during electro-thermal annealing (ETA), applying gate module engineering was more suitable than engineering the isolation or source drain modules.
Publisher
MDPI
Issue Date
2022-01
Language
English
Article Type
Article
Citation

MICROMACHINES, v.13, no.1

ISSN
2072-666X
DOI
10.3390/mi13010124
URI
http://hdl.handle.net/10203/292124
Appears in Collection
EE-Journal Papers(저널논문)
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