A Ka-band CMOS two-stage Doherty power amplifier (DPA) is presented, whose back-off efficiency is improved by voltage-mode Doherty load modulation. The input and output networks of its power stage are composed of transmission line transformers (TLTs) and single-ended Doherty networks implemented with lumped elements. An adaptive bias circuit to boost the Doherty operation is included in the gate network of the auxiliary amplifier. It shows a power gain of 16.2 dB with 48.2% peak drain efficiency (DE) and 25% 6-dB back-off DE at 26 GHz. It has two times higher 6-dB back-off efficiency in comparison to that of a theoretical class-A power amplifier. It is fabricated in a 28-nm bulk CMOS process and occupies 0.094-mm(2) core size.