Lateral profiling of gate dielectric damage by off-state stress and positive-bias temperature instability

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Gate dielectric degradation caused by off-state stress (OSS) and positive-bias temperature instability (PBTI) was analyzed in terms of charge trapping inside the gate dielectric and at the interface. Under the same degree of stress voltage, the OSS damage caused more degradation of threshold voltage (VT) than the PBTI damage. When the two stresses were alternately applied to an n-channel MOSFET, they effectively produced a leftward shift in the VT. This was because a greater negative VT shift was produced by the OSS and a less positive VT shift was produced by the PBTI. By analyzing the characteristics of the gate induced drain leakage (GIDL), it was determined that charge trapping inside the gate dielectric was more localized on the drain side than on the source side after OSS, but was distributed at a relatively similar level along the channel length direction after PBTI. To analyze the interface traps caused by OSS and PBTI, charge pumping (CP) measurements were conducted to map their lateral distribution along the channel direction. The PBTI-induced interface traps were found to be symmetrically distributed on the source side and drain side, while the OSS-induced interface traps were more concentrated toward the drain side.
Publisher
PERGAMON-ELSEVIER SCIENCE LTD
Issue Date
2021-12
Language
English
Article Type
Article
Citation

MICROELECTRONICS AND RELIABILITY, v.127, pp.114383

ISSN
0026-2714
DOI
10.1016/j.microrel.2021.114383
URI
http://hdl.handle.net/10203/288060
Appears in Collection
EE-Journal Papers(저널논문)
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