Off-state leakage in MOSFET considering source/drain extension regions

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Transistors have reached the extremely small dimensions of sub-10 nm in this era. Gate length has always been primarily considered for the scaling-down of CMOS technologies, but the total contacted poly pitch is the key to achieving a high packing density chip. In this work, the source/drain extension region is taken into consideration to investigate off-state leakage, especially for band-to-band tunneling and Schottky tunneling leakage. Various device parameters were modified within the dimensions of state-of-the-art transistors in the latest semiconductor roadmap. This study was carried out with the aid of the TCAD simulator calibrated using nonequilibrium Green's function simulation.
Publisher
IOP PUBLISHING LTD
Issue Date
2021-08
Language
English
Article Type
Article
Citation

SEMICONDUCTOR SCIENCE AND TECHNOLOGY, v.36, no.8, pp.085018

ISSN
0268-1242
DOI
10.1088/1361-6641/ac0757
URI
http://hdl.handle.net/10203/286950
Appears in Collection
EE-Journal Papers(저널논문)
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