All-Solid-State Ion Synaptic Transistor for Wafer-Scale Integration with Electrolyte of a Nanoscale Thickness

Cited 1 time in webofscience Cited 0 time in scopus
  • Hit : 68
  • Download : 0
Neuromorphic hardware computing is a promising alternative to von Neumann computing by virtue of its parallel computation and low power consumption. To implement neuromorphic hardware based on deep neural network (DNN), a number of synaptic devices should be interconnected with neuron devices. For ideal hardware DNN, not only scalability and low power consumption, but also a linear and symmetric conductance change with a large number of conductance levels is required. Here, an all-solid-state polymer electrolyte-gated synaptic transistor (pEGST) is fabricated on an entire silicon wafer with CMOS microfabrication and initiated chemical vapor deposition process. The pEGST shows good linearity as well as symmetry in potentiation and depression, conductance levels up to 8,192, and low switching energy smaller than 20 fJ pulse(-1). Selected 128 levels from 8,192 are used to identify handwritten digits in the MNIST database with the aid of a multilayer perceptron, resulting in a recognition rate of 91.7%.
Publisher
WILEY-V C H VERLAG GMBH
Issue Date
2021-06
Language
English
Article Type
Article
Citation

ADVANCED FUNCTIONAL MATERIALS, v.31, no.23, pp.2010971

ISSN
1616-301X
DOI
10.1002/adfm.202010971
URI
http://hdl.handle.net/10203/285604
Appears in Collection
EE-Journal Papers(저널논문)CBE-Journal Papers(저널논문)
Files in This Item
There are no files associated with this item.
This item is cited by other documents in WoS
⊙ Detail Information in WoSⓡ Click to see webofscience_button
⊙ Cited 1 items in WoS Click to see citing articles in records_button

qr_code

  • mendeley

    citeulike


rss_1.0 rss_2.0 atom_1.0