LDPC decoder, semiconductor memory system and operating method thereofLDPC 디코더, 반도체 기억 장치 시스템과 이의 작동 방법

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A semiconductor memory system including: a semiconductor memory device suitable for storing a codeword; and an LDPC decoder suitable for decoding the codeword to generate decoded data, wherein the LDPC decoder includes: a message passing decoding component suitable for performing a first decoding operation of decoding the codeword, and calculating the minimum value among numbers of UCNs; and an error path detection component suitable for detecting error path candidates using a tree in which each of UCNs corresponding to the minimum value is set to a root node, sorting the detected error path candidates in ascending order of maximum LLRs, resetting symbol values and LLRs of variable nodes in the error path candidates, and providing the message passing decoding unit with information on the reset symbol values and LLRs.
Assignee
KAIST, SK Hynix Inc.
Country
US (United States)
Application Date
2019-11-21
Application Number
16691278
Registration Date
2021-05-04
Registration Number
10997021
URI
http://hdl.handle.net/10203/285540
Appears in Collection
EE-Patent(특허)
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