A D-Band High-Gain and Low-Power LNA in 65-nm CMOS by Adopting Simultaneous Noise- and Input-Matched G(max)-Core

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This article proposes a high-gain and low-power low-noise amplifier (LNA) by adopting a simultaneous noise- and input-matched (SNIM) maximum achievable gain (G(max)) core. The G(max)-core is implemented by adjusting the infinite combinations of embedding networks with three passive elements. Based on the proposed two-port noise analysis for implementing the G(max)-core, the input stage Gmax-core can achieve a simultaneous power gain and noise matching. The adoption of the G(max)-core in the input stage can maximize the amount of gain per stage, leading to higher total power gain and lower noise figure (NF). The two-stage 150-GHz LNA adopting the SNIM G(max)-core is implemented in a 65-nm CMOS process. The measurement results show a peak gain of 17.9 dB at 152.2 GHz, 3-dB bandwidth of 11 GHz, NF of 4.7 and 6.2 dB at 148 and 150 GHz, respectively, and a peak power added efficiency (PAE) of 7.7% while dissipating only 13.73 mW. This work shows the highest gain per stage and the lowest NF with the lowest dc power consumption among other reported CMOS D-band amplifiers.
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Issue Date
2021-05
Language
English
Article Type
Article
Citation

IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, v.69, no.5, pp.2519 - 2530

ISSN
0018-9480
DOI
10.1109/TMTT.2021.3066972
URI
http://hdl.handle.net/10203/285460
Appears in Collection
EE-Journal Papers(저널논문)
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