A 43.1TOPS/W Energy-Efficient Absolute-Difference-Accumulation Operation Computing-In-Memory With Computation Reuse

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dc.contributor.authorUm, Soyeonko
dc.contributor.authorKim, Sangyeobko
dc.contributor.authorKim, Sangjinko
dc.contributor.authorYoo, Hoi-Junko
dc.date.accessioned2021-06-01T02:10:24Z-
dc.date.available2021-06-01T02:10:24Z-
dc.date.created2021-06-01-
dc.date.created2021-06-01-
dc.date.issued2021-05-
dc.identifier.citationIEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.68, no.5, pp.1605 - 1609-
dc.identifier.issn1549-7747-
dc.identifier.urihttp://hdl.handle.net/10203/285390-
dc.description.abstractRecently, Computing-In-Memory (CIM) processors have been proposed to achieve high energy-efficiency by reducing data movement and solving memory bottlenecks. Furthermore, a network with high accurate image classification has been introduced through the Absolute-Difference-Accumulation (ADA) operation instead of the multiplication-and-accumulation operation, which is widely used in DNN. ADA operation provides not only opportunities for high energy-efficient DNN accelerating by reducing multiplication but also a chance to reuse computation results. However, the previous CIM processor cannot reuse previous computation results for other computations. In this brief, we propose a high accurate and high energy-efficient ADA-CIM processor that with two key features: 1) computation reuse for low-power, resulting in a 49.5% CIM operation power reduction, and 2) low-cost sign prediction core with 3-bit activation and weight quantization for high utilization. From the two key features, the proposed ADA-CIM processor is simulated in 28 nm CMOS technology and occupies 3.78 mm(2). It consumes 2.77mW and achieves 43.1 TOPS/W energy-efficiency with a high-accuracy of 91.62% at CIFAR-10 (ResNet-20).-
dc.languageEnglish-
dc.publisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC-
dc.titleA 43.1TOPS/W Energy-Efficient Absolute-Difference-Accumulation Operation Computing-In-Memory With Computation Reuse-
dc.typeArticle-
dc.identifier.wosid000645863300010-
dc.identifier.scopusid2-s2.0-85103250029-
dc.type.rimsART-
dc.citation.volume68-
dc.citation.issue5-
dc.citation.beginningpage1605-
dc.citation.endingpage1609-
dc.citation.publicationnameIEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS-
dc.identifier.doi10.1109/TCSII.2021.3067327-
dc.contributor.localauthorYoo, Hoi-Jun-
dc.contributor.nonIdAuthorUm, Soyeon-
dc.description.isOpenAccessN-
dc.type.journalArticleArticle-
dc.subject.keywordAuthorRandom access memory-
dc.subject.keywordAuthorProgram processors-
dc.subject.keywordAuthorEnergy efficiency-
dc.subject.keywordAuthorCommon Information Model (computing)-
dc.subject.keywordAuthorQuantization (signal)-
dc.subject.keywordAuthorComputer architecture-
dc.subject.keywordAuthorCircuits and systems-
dc.subject.keywordAuthorAbsolute-difference-accumulation (ADA) operation-
dc.subject.keywordAuthorcomputation reuse-
dc.subject.keywordAuthorcomputing-in-memory (CIM)-
dc.subject.keywordAuthorenergy-efficient-
dc.subject.keywordAuthorlow-cost absolute difference sign prediction-
dc.subject.keywordAuthorSRAM-
dc.subject.keywordPlusSRAM-
dc.subject.keywordPlusMACRO-
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