Electrical characterization and neuromorphic application of 3-dimensional semiconductor devices

Abstract

Semiconductor transistors have been continuously scaled down for higher performance and better productivity, and a gate-all-around (GAA) structure has been proposed and is being investigated as one of the effective methods to control the leakage current caused by size reduction. In the semiconductor industry, GAA structure has already been applied to logic chips using transistors having the smallest gate length, and NAND flash memory devices have begun to adopt a GAA structure with a three-dimensional structure. In DRAM chips, vertical GAA devices are being studied as candidates for future DRAM cell transistors for optimization of capacitors and cell transistors.In addition, due to the continuous size reduction of a transistor, the variability in the fabrication process has a greater influence on the variation of the characteristics between the devices. To solve this problem, a junctionless structure has been proposed. Unlike the conventional structure using inversion, channel and source and drain are formed by ion-implantation at once. Therefore, it is a structure that improves the variation of the effective channel length of the transistors.In the first part of the chapter 2, the hot-carrier degradation of the junctionless mode (JM) and the inversion mode (IM) of 5-story vertically integrated GAA MOSFETs is investigated for the first time. The gate and drain voltage conditions with the worst drain current degradation due to hot-carriers were confirmed and the lifetimes were calculated and compared. It is found that the degradation of drain current induced by the hot-carrier injection (HCI) in the JM-FET is less than that in the IM-FET for the same dimensions and bias conditions, because of the bulk conduction mechanism of the JM-FET, which is in contrast to surface conduction of the IM-FET. The results are obtained using electrical measurements and numerical simulations. In addition, differences in the diameters of nanowire and channel doping concentrations were predicted. The analysis of how HCI affects the lifetime reliability of vertically integrated GAA MOSFETs is of great importance for ultimate scaling of the silicon transistor.In the second part of the chapter 2, in the gate-all-around transistors using the same 5-story vertically integrated nanowires, program and erase operations for the flash memory operation of the Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) transistors with a gate dielectric material of SiO2-SiNx-SiO2 structure were evaluated. Since the floating body effect occurs in a SONOS flash memory transistor with a conventional IM-FET, the efficiency of the erase operation is reduced. The program and erase operations in the JM-FET, which is expected to have no floating body effect, are compared with the IM-FET. The operations by the drain electrode, which is used in the 3D NAND flash memory cell transistors, were compared with those by the conventional gate electrode.In the chapter 3, transistors as synaptic devices for the neuromorphic system, which can be used for future artificial intelligence systems, were investigated. The operations required for the synaptic device are potentiation and depression, which change the conductivity through repeated input of pulses for multi-level state. The potentiation and depression operation were evaluated by using transistors with a BE-SONOS structure, which can improve the efficiency of the erase operation, and with a vertical silicon pillar as a channel and a gate of the GAA structure. Since the curves of the results of the potentiation and depression operations require linearity and symmetry, the optimum condition was found by applying pulses of various voltage and time conditions, and the gate voltage condition for reading the conductivity was also confirmed. The linearity of the curves was evaluated for each condition, fitting process for synaptic operation was performed, and finally the recognition rates of the characters of MNIST set, were compared.In the chapter 4, silicon semiconductor based neuromorphic synaptic devices were investigated. The root cause of the linearity of the synaptic device shown in the previous chapter 3 was confirmed by simulation and theoretical approach. Based on the results, a planar FET named TriNo-FET was fabricated. During the fabrication of three planar TriNo-FETs, experiments with charge trap layers were also carried out to optimize the process conditions and further improve the conventional TriNo-FET. Under optimized conditions, the improvement of the neuromorphic synaptic device characteristics of the TriNo-FET was confirmed by electrical measurements. Finally, by fabricating a FinFET-structured TriNo-FET with a further reduced minimum gate length, it was confirmed that the TriNo-FETs with gate lengths of 100 nm or less can operate as synaptic devices.