Analysis and design of a low spur phase-locked loop

Abstract

In this dissertation, two types of low spur frequency synthesizers are proposed. One is a fractional-N digital phase-locked loop (DPLL), and the other is a fractional-N analog phase-locked loop (APLL). For the proposed DPLL, a frequency multiplier time-to-digital converter (FMTDC) and a static phase error canceller (SPEC) are proposed. The FMTDC simultaneously acts as both a frequency multiplier and a time-to-digital converter. The SPEC cancels out the static phase error that causes a reference spur. In the proposed DPLL, the measured integrated RMS jitter is 684.4fs from 100Hz to 40MHz when its output frequency is about 5.4GHz. Its measured reference spur is about -95.4dBc. For the proposed APLL, a dual feedback loop APLL consists of a phase locked loop and a frequency locked loop for reducing the fractional spurs. And, a reduced pulse width frequency-to-voltage converter(F2V) is proposed. In the proposed APLL, the measured integrated RMS jitter is 5.91ps from 100Hz to 40MHz when its output frequency is about 6.1GHz. Its measured fractional spur is reduced about by 14.36dBc when the FLL is turned on.