Analysis and design of a low spur phase-locked loop낮은 스퍼를 갖는 위상 동기 루프의 분석 및 설계

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dc.contributor.advisorCho, SeongHwan-
dc.contributor.authorKim, Hyojun-
dc.description학위논문(박사) - 한국과학기술원 : 전기및전자공학부, 2020.8,[vii, 77 p. :]-
dc.description.abstractIn this dissertation, two types of low spur frequency synthesizers are proposed. One is a fractional-N digital phase-locked loop (DPLL), and the other is a fractional-N analog phase-locked loop (APLL). For the proposed DPLL, a frequency multiplier time-to-digital converter (FMTDC) and a static phase error canceller (SPEC) are proposed. The FMTDC simultaneously acts as both a frequency multiplier and a time-to-digital converter. The SPEC cancels out the static phase error that causes a reference spur. In the proposed DPLL, the measured integrated RMS jitter is 684.4fs from 100Hz to 40MHz when its output frequency is about 5.4GHz. Its measured reference spur is about -95.4dBc. For the proposed APLL, a dual feedback loop APLL consists of a phase locked loop and a frequency locked loop for reducing the fractional spurs. And, a reduced pulse width frequency-to-voltage converter(F2V) is proposed. In the proposed APLL, the measured integrated RMS jitter is 5.91ps from 100Hz to 40MHz when its output frequency is about 6.1GHz. Its measured fractional spur is reduced about by 14.36dBc when the FLL is turned on.-
dc.subjectPhase locked loop (PLL)▼aAnalog PLL▼aDigital PLL▼aFractional-N PLL▼aFrequency multiplier▼aTime-to-Digital Converter▼aFractional spur▼aReference spur▼aLow noise-
dc.subject위상동기루프▼a아날로그 위상 동기 루프▼a디지털 위상 동기 루프▼aN-분수 위상 동기 루프▼a주파수 체배기▼a시간-디지털 변환기▼a기준 주파수 스퍼▼a비정수 스퍼▼a저잡음-
dc.titleAnalysis and design of a low spur phase-locked loop-
dc.title.alternative낮은 스퍼를 갖는 위상 동기 루프의 분석 및 설계-
dc.description.department한국과학기술원 :전기및전자공학부,-
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