The demand for the increased memory size in the computer industry and the scalability challenges of the traditional memory technologies inspired the researches towards next-generation memory technologies. As a promising candidate, spin-transfer torque random access memory (STT-RAM) have emerged that leverage high density, non-volatility, fast access time, and good CMOS process compatibility. The reliability, large write energy consumption, and high write latency of STT-RAMs are the major bottlenecks in the commercial deployment of STT-RAM caches. In recent years, significant research has been conducted to improve storage density and to further enhance the scalability of STT-RAMs. This results in reduced switching current and switching latency of STT-RAM devices. However, reliability is severely degraded by the current trend of technology scaling. The reliability of STT-RAMs is affected by environmental fluctuations, process variations, and intrinsic device operating uncertainties. The effect of these phenomenons becomes more severe with technology scaling.
Moreover, the continuous increasing of tunnel magneto-resistance (TMR) ratio of the MTJ motivated the development of multi-level cell (MLC) STT-RAM, which allows storing multiple data bits in a single memory cell. Two types of MLC STT-RAM cells, termed as, series MLC and parallel MLC, have been proposed. However, the MLC STT-RAM further adds to the energy consumption, performance, and reliability issues of STT-RAM.
The one objective of the dissertation is to reduce the cost of handling the high error rate in STT-RAM caches. Further, in this dissertation, we propose a scheme that aims to overcome the reliability issues of STT-RAM caches and also address the additional performance, energy and reliability bottlenecks of MLC STT-RAM. We propose the following scheme.
● A Restore-free Mode for MLC STT-RAM Caches.
● Mitigating Read and Write Errors in STT-RAM Caches with Low-cost ECC.
The first scheme targets the two-step read and write operations in MLC STT-RAM caches that incur significant energy and performance overheads. Further, this scheme also reduces the performance and energy overhead of handling read errors in MLC STT-RAM caches. Our proposed scheme achieves a 27.4% (23%) dynamic energy reduction, a 3.7% (7%) increase in performance, and an 81% (62.5%) lifetime improvement, in single-core (quad-core) systems.
In the second scheme, we propose to overcome the performance overhead in simultaneously handling the read and write errors in single-level cell (SLC) STT-RAM. Our proposed scheme makes use of low-cost, many-bit ECC. The evaluation results show that our proposed scheme achieves performance close to that of an error-free cache by improving performance by 13% (16%) over the baseline scheme in single-core (quad-core) systems while requiring 50% less storage space for the ECC parity bits.