Hardware support for transactions in persistent memory

Abstract

Non-Volatile Memory (NVM) technology has emerged and is now available in the market. With this technology, in-memory systems replace their persistent storage to NVM and support data availability and durability. Since NVM has characteristics of both memory and storage, the granularity of data to be durable and persistent is shifting from the coarse-grain one (e.g., block I/O) to the fine-grain one (e.g., instruction). As the data become durable with fine-granularity, applications can reduce write amplification and remove block I/O overheads. Furthermore, it enables instant restart on system reboot and snapshots in very short windows. However, per-instruction durability requires cache-flush and store-fence operations for every store instruction. Therefore, this model brings substantial performance overheads and also is poor in terms of usability. Programmer-defined failure-atomic sections (e.g., FASEs) are introduced to provide better performance and usability. Instructions in FASEs can execute without cache-flush and store-fence except at the end of FASEs, so that improves both performance and usability. FASE-based programming becomes prominent in persistent data structures. This resembles database transactions in terms of needs for supporting transactional semantics such as atomicity, consistency, isolation, and durability. However, guaranteeing full ACID properties in NVM is challenging. In this dissertation, we define two requirements for supporting FASE-based transactions in persistent memory. First, updates to NVM need to be atomic and durable. Traditionally, the volatile-persistent boundary was lying between DRAM and HDD (or SSD), and data durability and atomic updates are responsible for filesystems in the OS. However, NVM blurs this boundary. As a result, partial updates leave data inconsistent states, and applications are responsible for guaranteeing atomic and durable updates. Supporting atomic durability in emerging persistent memory requires data consistency across potential system failures. For atomic durability support in the nonvolatile memory, the traditional write-ahead log (WAL) technique has been employed to guarantee the persistence of logs before actual data updates. Based on the WAL mechanism, recent studies proposed HW-assisted logging techniques with undo, redo, or undo+redo principles. The HW log manager accelerates atomic durable updates by allowing the overlapping of log writing and transaction execution as long as the atomicity invariant can be satisfied. Although both log and data write must be optimized, the prior studies exhibit trade-offs in performance under various access patterns. The undo approach experiences performance degradation due to synchronous in-place data updates since the log contains only the old values. On the other hand, the undo+redo approach stores both old and new values, and does not require synchronous in-place data updates. However, the larger log size increases the amount of log writes, which diminishes the benefits of asynchronous data updates. The prior redo approach demands extra NVM read bandwidth to fetch NVM log entries for indirectly updating in-place data. To overcome the limitations of the previous approaches, this paper proposes novel redo-based logging (ReDU), which performs direct and asynchronous in-place data update to NVM. The use of DRAM not only improves the throughput of FASE-based transactions but also reduces the complexity of HW-assisted logging. ReDU exploits a small region of DRAM as a write-cache to remove NVM writes from the critical path. The experimental results show that the proposed logging mechanism provides the best performance under a variety of write patterns compared to the previous undo, redo, and undo+redo approaches. The second requirement of supporting transactions in NVM is to guarantee serializability. Although hardware transactional memory (HTM) is a promising solution for concurrency control, it has the fundamental limitation, which bounds the transaction in the on-chip cache. HTM is known to be only efficient for small transactions, in which footprints fit in the transaction boundary (e.g., the private L1 cache). Once the transaction exceeds beyond the limitation, which we referred to as capacity overflows, it should abort and restart since transactional systems no longer can function correctly. Furthermore, it is recommended to handle overflowed transactions by serializing execution, instead of retrying, which substantially degrades the concurrency. To this end, we propose Unbounded and Persistent hardware Transactional Memory (UP-TM) that supports unlimited sizes of transactions without overflows. UP-TM, first, detects conflicts among transactions beyond LLC and for both DRAM and NVM. Conflict detection is based on cache-coherence protocol but extended with signatures that successfully detect all conflicts even cache blocks are not present in on-chip caches. In addition, UP-TM supports atomic durable ReDU for buffering speculative data within transactions and uses the undo-based log for non-persistent (DRAM) data for short commit latency. The evaluation with the hybrid key-value store as well as persistent or volatile transactions, UP-TM outperforms the LLC-bounded HTM that serializes execution if a transaction has overflowed from LLC.