Advanced interconnect engineering for porous ultralow-k dielectrics and beyond Cu metallization

Abstract

As critical dimensions (CD) in modern integrated circuit (IC) chips have been already reduced to a few tens of nanometer scales, both of interconnect resistance (R) and capacitance (C) increase, which causes a severe RC-delay problem. The increase in C has been suppressed by introducing porosity in dielectrics to reduce effective dielectric constant. However, the porosity causes many side-effects especially for the process compatibility, such as mechanical/chemical-strength weakening, vulnerability to plasma-induced damage, and penetration of barrier/liner precursors. In case of R, the scaling of CD inherently increases the resistivity of Cu, since the CD in modern ICs is comparable or even smaller than bulk electron mean-free-path of Cu. This fundamental physics makes exponential increase in interconnect resistance inevitable.

In this dissertation, both issues in C and R will be addressed. In case of C, A novel solution to enable highly porous ultralow-k dielectrics will be discussed. By introducing initialed chemical vapor deposition (iCVD) technology, it will be shown that surface-limited pore-sealing of highly porous ultralow-k dielectrics is possible. Comprehensive evaluation of the dielectric properties will be followed. In case of R, Ruthenium (Ru) will be considered as an alternative conductor to replace current Cu interconnects. Combined with a new subtractive etch process scheme, in-depth study about Ru resistivity will be shown.