(A) pin-efficient PAM-4 single-ended transceiver with 5-Bit 4-Wire balanced coding for parallel electrical link

Abstract

As information and communication technology develops, global IP traffic is increasing incessantly over the past-decades. In order to process the large amount of data at fast speed, high-bandwidth devices are highly in demand. On the other hand, interconnect channel has not been developed at the same-rate and became a major bottleneck for high-bandwidth operation, imposing higher loss to the signal being transmitted. The trend to overcome the channel loss is to use multi-level PAM signaling (e.g. PAM-4) which results in improved spectral efficiency. However, multi-level PAM signaling has rarely been employed in single-ended memory interface due to several difficulties such as noise, interference and linearity. In this thesis, a new balanced-coding technique and transceiver architecture have been proposed to overcome the following difficulties in single-ended interface and to achieve high pin-efficiency. Based on the proposed coding scheme, single-ended PAM-4 transceiver is implemented.