DC Field | Value | Language |
---|---|---|
dc.contributor.author | Kareem, Pervaiz | ko |
dc.contributor.author | Shin, Youngsoo | ko |
dc.date.accessioned | 2021-03-11T05:10:06Z | - |
dc.date.available | 2021-03-11T05:10:06Z | - |
dc.date.created | 2021-03-11 | - |
dc.date.issued | 2021-02 | - |
dc.identifier.citation | IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, v.34, no.1, pp.49 - 57 | - |
dc.identifier.issn | 0894-6507 | - |
dc.identifier.uri | http://hdl.handle.net/10203/281482 | - |
dc.description.abstract | Diversity of test patterns is important for many lithography applications. It is however difficult to achieve with sample layouts or by using a popular pattern generator. We propose a synthesis method of lithography test patterns. Each pattern is represented by a map of IPS (image parameter space) values, called IPS map. A key in the proposed method is to guarantee that the center of the synthesized pattern corresponds to the IPS values given as input. The synthesis consists of three steps: a new IPS map is generated using an adversarial auto-encoder (AAE) with given IPS values; the IPS map is converted to its corresponding layout through an auto-encoder (AE); the layout goes through the final processing to remove any unrealistic shapes. Both AAE and AE are trained beforehand by using a few sample layouts. The synthesis method is applied to lithography modeling. The RMSE of lithography model is reduced by 30% when the model is calibrated with synthesized patterns, compared to the model based on test patterns from a pattern generator. A machine learning-based lithography simulation is taken as a second application. When the synthesized patterns are used to train the machine learning model, the accuracy of lithography simulation improves by 7%. | - |
dc.language | English | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.title | Synthesis of Lithography Test Patterns Using Machine Learning Model | - |
dc.type | Article | - |
dc.identifier.wosid | 000615040700007 | - |
dc.identifier.scopusid | 2-s2.0-85099725792 | - |
dc.type.rims | ART | - |
dc.citation.volume | 34 | - |
dc.citation.issue | 1 | - |
dc.citation.beginningpage | 49 | - |
dc.citation.endingpage | 57 | - |
dc.citation.publicationname | IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING | - |
dc.identifier.doi | 10.1109/TSM.2021.3052302 | - |
dc.contributor.localauthor | Shin, Youngsoo | - |
dc.description.isOpenAccess | N | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | IP networks | - |
dc.subject.keywordAuthor | Layout | - |
dc.subject.keywordAuthor | Generators | - |
dc.subject.keywordAuthor | Image reconstruction | - |
dc.subject.keywordAuthor | Lithography | - |
dc.subject.keywordAuthor | Standards | - |
dc.subject.keywordAuthor | Gaussian distribution | - |
dc.subject.keywordAuthor | Lithography test patterns | - |
dc.subject.keywordAuthor | pattern synthesis | - |
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