A Ka-band CMOS cascode power amplifier (PA) linearized with a cold-FET-based interstage matching network is presented, which is designed in a 65-nm CMOS process. Since it is difficult to make a cascode PA matched to the optimum output and input impedances at high frequencies, a matching network has to be introduced at the node between the commonsource (CS) and common-gate (CG) stages. The cold-FET-based matching network improves the linearity and the input and output impedance matchings, which is analyzed and optimized with its simple model. It makes the PA have gain expansion and phase lag with the power, which allows the PA to have less amplitude-to-amplitude (AM-AM) and amplitude-to-phase (AM-PM) distortions. In addition, it improves the return losses of the PA by making the impedances for power matching and conjugate matching located closely. The implemented PA achieves the peak power-added efficiency (PAE) of 38.2% and the saturated output power (P-sat) of 17.1 dBm at 31 GHz while occupying the chip area of 0.16 mm(2). It is also shown that the OP1dB is improved by 1.7 dB, and the AM-PM distortion is reduced to only 1.1 degrees due to the linearization technique. It is tested with 64-quadrature amplitude modulation (QAM) signals, which has a 400-MHz channel bandwidth (BW) and a 9.7-dB peak-to-average power ratio (PAPR). It achieves average output powers of 9.6/7.7 dBm with error vector magnitudes (EVMs) of -25/-30 dB for 64-QAM OFDM signals, efficiencies of 17.7%/12%, and the adjacent channel leakage ratio (ACLR) of -28.2/-32.8 dBc, respectively.