A 7.86 mW +12.5 dBm in-band IIP3 8-to-320 MHz capacitive harmonic rejection mixer in 65nm CMOS

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We present a low-power high-linearity capacitive harmonic rejection mixer for cognitive radio applications. A passive mixer first receiver with capacitive 16-phase sinusoidal weighting implements harmonic rejection down-conversion, and an AC-coupled fully differential capacitor feedback transimpedance amplifier provides baseband linear voltage gain and band-pass filtering achieving an in-band IIP3 of +12.5 dBm at 320 MHz LO over 3 MHz baseband. The 1.62mm
Publisher
IEEE Computer Society
Issue Date
2014-09
Language
English
Citation

40th European Solid-State Circuit Conference, ESSCIRC 2014, pp.227 - 230

DOI
10.1109/ESSCIRC.2014.6942063
URI
http://hdl.handle.net/10203/280348
Appears in Collection
BiS-Conference Papers(학술회의논문)
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