3.125-to-28.125 Gb/s 4.72 mW/Gb/s Multi- Standard Parallel Transceiver Supporting Channel-Independent Operation in 40-nm CMOS

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This paper presents a 3.125-to-28.125 Gb/s dual-lane multi-standard parallel transceiver supporting channel-independent operation. Network equipment supports multiple data rates to encompass diversified communication standards. However, network equipment supports only a fixed number of channels at each supported data rate. This lack of flexibility limits the utilization rate of the network equipment. This study proposes a clock and data recovery (CDR) IC to obtain utilization flexibility and scalability in each channel with complete channel independency. The CDR IC achieves a wide tuning capability for data rates ranging from 3.125 to 28.125 Gb/s with low clock jitter owing to the use of injection-locked oscillators in each channel. Each CDR lane generates a channel-independent injection clock signal with a fixed-frequency global clock signal using a variable clock divider and a phase rotator with the proposed harmonic distortion compensator. In addition, a frequency tracking loop is proposed using a bang-bang phase detector-based natural frequency detector to align the natural frequency of the injection-locked oscillator with the input data rate, thereby suppressing the injection spur. The test chip fabricated in a 40 nm CMOS exhibits a power efficiency of 4.72 mW/Gb/s, while generating a recovered clock jitter of 976 fs(rms) at a data rate of 25.78125 Gb/s.
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Issue Date
2020-08
Language
English
Article Type
Article
Citation

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, v.67, no.8, pp.2647 - 2658

ISSN
1549-8328
DOI
10.1109/TCSI.2020.2980139
URI
http://hdl.handle.net/10203/275964
Appears in Collection
EE-Journal Papers(저널논문)
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