A Framed-Pulsewidth Modulation Transceiver for High-Speed Broadband Communication Links

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dc.contributor.authorJeon, Sejunko
dc.contributor.authorKwon, Woohyunko
dc.contributor.authorYoon, Jong-Hyeokko
dc.contributor.authorYoon, Taehunko
dc.contributor.authorKwon, Kyeonghako
dc.contributor.authorYang, Jaehyeokko
dc.contributor.authorBae, Hyeon-Minko
dc.date.accessioned2020-08-20T08:55:13Z-
dc.date.available2020-08-20T08:55:13Z-
dc.date.created2020-08-18-
dc.date.created2020-08-18-
dc.date.issued2020-08-
dc.identifier.citationIEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, v.67, no.8, pp.2825 - 2835-
dc.identifier.issn1549-8328-
dc.identifier.urihttp://hdl.handle.net/10203/275895-
dc.description.abstractA 20 Gb/s serial link transceiver employing a framed-pulsewidth modulation (FPWM) scheme that overcomes the signal-to-noise (SNR) degradation without a linearity requirement is presented. The FPWM scheme encodes data at the location and the width of the pulses in a frame spanning multiple unit intervals (UI) while maintaining a minimum pulsewidth equal to 1 UI. The test chip achieves a coding gain of 33 %, which allows a total throughput of 20 Gb/s while keeping the baud rate of 15 Gb/s. The equalization core incorporating programmable 3-tap pre-emphasis at the transmitter and a continuous-time linear equalizer (CTLE) at the receiver compensates for the channel insertion loss up to 12 dB at the baud frequency, and achieves < 10(-12) of bit error rate (BER). The transceiver IC, fabricated in 40 nm CMOS, occupies 2.2x 0.48 mm(2) and consumes 90.6 mW from a 0.9 V supply which renders the power efficiency of 4.53 mW/Gb/s.-
dc.languageEnglish-
dc.publisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC-
dc.titleA Framed-Pulsewidth Modulation Transceiver for High-Speed Broadband Communication Links-
dc.typeArticle-
dc.identifier.wosid000554901800027-
dc.type.rimsART-
dc.citation.volume67-
dc.citation.issue8-
dc.citation.beginningpage2825-
dc.citation.endingpage2835-
dc.citation.publicationnameIEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS-
dc.identifier.doi10.1109/TCSI.2020.2982050-
dc.contributor.localauthorKwon, Kyeongha-
dc.contributor.localauthorBae, Hyeon-Min-
dc.contributor.nonIdAuthorYoon, Taehun-
dc.description.isOpenAccessN-
dc.type.journalArticleArticle-
dc.subject.keywordAuthorModulation-
dc.subject.keywordAuthorframe-
dc.subject.keywordAuthortransceiver-
dc.subject.keywordAuthorserdes-
dc.subject.keywordAuthorI/O-
dc.subject.keywordAuthorinterconnect-
dc.subject.keywordAuthorspectral efficiency-
dc.subject.keywordAuthorclock and data recovery (CDR)-
dc.subject.keywordAuthorencoder-
dc.subject.keywordAuthordecoder-
dc.subject.keywordAuthorserial link-
dc.subject.keywordAuthorwireline-
dc.subject.keywordAuthorequalization-
dc.subject.keywordPlusCOMPENSATION-
dc.subject.keywordPlusTRANSMITTER-
dc.subject.keywordPlusDUOBINARY-
dc.subject.keywordPlusRECEIVER-
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