DC Field | Value | Language |
---|---|---|
dc.contributor.author | Jeon, Sejun | ko |
dc.contributor.author | Kwon, Woohyun | ko |
dc.contributor.author | Yoon, Jong-Hyeok | ko |
dc.contributor.author | Yoon, Taehun | ko |
dc.contributor.author | Kwon, Kyeongha | ko |
dc.contributor.author | Yang, Jaehyeok | ko |
dc.contributor.author | Bae, Hyeon-Min | ko |
dc.date.accessioned | 2020-08-20T08:55:13Z | - |
dc.date.available | 2020-08-20T08:55:13Z | - |
dc.date.created | 2020-08-18 | - |
dc.date.created | 2020-08-18 | - |
dc.date.created | 2020-08-18 | - |
dc.date.created | 2020-08-18 | - |
dc.date.created | 2020-08-18 | - |
dc.date.issued | 2020-08 | - |
dc.identifier.citation | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, v.67, no.8, pp.2825 - 2835 | - |
dc.identifier.issn | 1549-8328 | - |
dc.identifier.uri | http://hdl.handle.net/10203/275895 | - |
dc.description.abstract | A 20 Gb/s serial link transceiver employing a framed-pulsewidth modulation (FPWM) scheme that overcomes the signal-to-noise (SNR) degradation without a linearity requirement is presented. The FPWM scheme encodes data at the location and the width of the pulses in a frame spanning multiple unit intervals (UI) while maintaining a minimum pulsewidth equal to 1 UI. The test chip achieves a coding gain of 33 %, which allows a total throughput of 20 Gb/s while keeping the baud rate of 15 Gb/s. The equalization core incorporating programmable 3-tap pre-emphasis at the transmitter and a continuous-time linear equalizer (CTLE) at the receiver compensates for the channel insertion loss up to 12 dB at the baud frequency, and achieves < 10(-12) of bit error rate (BER). The transceiver IC, fabricated in 40 nm CMOS, occupies 2.2x 0.48 mm(2) and consumes 90.6 mW from a 0.9 V supply which renders the power efficiency of 4.53 mW/Gb/s. | - |
dc.language | English | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.title | A Framed-Pulsewidth Modulation Transceiver for High-Speed Broadband Communication Links | - |
dc.type | Article | - |
dc.identifier.wosid | 000554901800027 | - |
dc.identifier.scopusid | 2-s2.0-85089908772 | - |
dc.type.rims | ART | - |
dc.citation.volume | 67 | - |
dc.citation.issue | 8 | - |
dc.citation.beginningpage | 2825 | - |
dc.citation.endingpage | 2835 | - |
dc.citation.publicationname | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS | - |
dc.identifier.doi | 10.1109/TCSI.2020.2982050 | - |
dc.contributor.localauthor | Kwon, Kyeongha | - |
dc.contributor.localauthor | Bae, Hyeon-Min | - |
dc.contributor.nonIdAuthor | Yoon, Taehun | - |
dc.description.isOpenAccess | N | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | Modulation | - |
dc.subject.keywordAuthor | frame | - |
dc.subject.keywordAuthor | transceiver | - |
dc.subject.keywordAuthor | serdes | - |
dc.subject.keywordAuthor | I/O | - |
dc.subject.keywordAuthor | interconnect | - |
dc.subject.keywordAuthor | spectral efficiency | - |
dc.subject.keywordAuthor | clock and data recovery (CDR) | - |
dc.subject.keywordAuthor | encoder | - |
dc.subject.keywordAuthor | decoder | - |
dc.subject.keywordAuthor | serial link | - |
dc.subject.keywordAuthor | wireline | - |
dc.subject.keywordAuthor | equalization | - |
dc.subject.keywordPlus | COMPENSATION | - |
dc.subject.keywordPlus | TRANSMITTER | - |
dc.subject.keywordPlus | DUOBINARY | - |
dc.subject.keywordPlus | RECEIVER | - |
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