Optimizing the Geometry of Chiral Magnetic Logic Devices

Abstract

We investigated how geometry affects chiral magnetic logic devices, using micro-magnetic simulation. The logical NOT gate in the device was operated by current-induced domain wall (DW) motion in perpendicularly magnetized nanowires with a locally modulated in-plane magnetic anisotropy (IMA) region, where the up-down DW is switched into a down-up DW by current. We modulated the width of the nanowires as well as the length of the IMA region and found that an optimized geometry exists which depends on the Dzyaloshinskii-Moriya Interaction. Integrating the optimized NOT-gate, we then demonstrated NAND or NOR logic operations. Our results provide design guidelines for the magnetic logic device, paving the way to functional magnetic logic-in-memory devices.