Layout Pattern Synthesis for Lithography Optimizations

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A set of comprehensive test patterns is important for a number of lithography applications. Pattern diversity is, however, hard to achieve either from parametric patterns or from actual patterns even though they are carefully extracted and classified. Automatic layout pattern synthesis is proposed in this paper. A generative adversarial network (GAN) is employed to generate a new set of discrete cosine transform (DCT) signals. It is converted to an image format through inverse DCT (IDCT). The image is blurred since output DCT signals from GAN correspond to lower frequency region. Another GAN, this time a conditional GAN (cGAN), is introduced to get sharpened layout pattern. A key in this process is to train the two GANs in such a way that generated patterns are different from existing actual patterns while they are still valid layouts. Experiments indicate that synthetic patterns are less redundant and cover 76% more space in image parameter set space than actual patterns. We choose a machine-learning guided OPC as an example application: when synthetic patterns are included to train OPC model, edge proximity error decreases by 21%. Resist model calibration is chosen as a second example: when synthetic patterns are combined with parametric- and real-patterns, CD RMSE decreases by 10.3%.
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Issue Date
2020-05
Language
English
Article Type
Article
Citation

IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, v.33, no.2, pp.283 - 290

ISSN
0894-6507
DOI
10.1109/TSM.2020.2982989
URI
http://hdl.handle.net/10203/274772
Appears in Collection
EE-Journal Papers(저널논문)
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