Charge-aware DRAM refresh reduction with value transformationCharge-aware DRAM refresh reduction with value transformation

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dc.contributor.author김세권ko
dc.contributor.authorKwak, Wonsangko
dc.contributor.author김창대ko
dc.contributor.author백대현ko
dc.contributor.authorHuh, Jaehyukko
dc.date.accessioned2020-06-11T01:21:05Z-
dc.date.available2020-06-11T01:21:05Z-
dc.date.created2020-06-10-
dc.date.created2020-06-10-
dc.date.issued2020-02-
dc.identifier.citation26th IEEE International Symposium on High Performance Computer Architecture, HPCA 2020, pp.663 - 676-
dc.identifier.urihttp://hdl.handle.net/10203/274616-
dc.description.abstractAs the memory capacity in a system has been growing, refresh operations consume increasing ratios of the total DRAM power. To reduce the power consumption of such refresh operations, this paper proposes a novel value-aware refresh reduction technique called ZERO - REFRESH which exploits zero values in memory contents. A DRAM cell can retain the discharged state without refresh operations, and ZERO - REFRESH skips refresh operations on rows with all discharged cells. For abundant unallocated memory pages in typical systems, the operating system fills them with zeros to clean the contents. For those idle pages, ZERO - REFRESH can eliminate refresh operations in an OS-transparent way without any new interface to DRAM. However, for allocated memory pages, memory contents may not have many consecutive zero values to match the refresh granularity of DRAM. To increase the frequency of zero values and to arrange them to match the refresh granularity, ZERO - REFRESH transforms the value of memory blocks to the base and delta values, inspired by the prior BDI (Base-Delta-Immediate) compression technique. Once values are converted, bits are transposed to be stored as consecutive discharged bits at the refresh granularity. Such value transformation and rearrangement can make the memory contents friendly to refresh reduction based on discharged cells. The experimental results based on simulation show that the DRAM refresh operations are reduced by 37% on average for a set of benchmark applications, if the entire memory is allocated for the applications. If the memory usage statistics collected from three data center traces are applied, the DRAM refresh operations can be reduced by 46%, 57%, and 83% respectively for the three scenarios.-
dc.languageEnglish-
dc.publisherInstitute of Electrical and Electronics Engineers Inc.-
dc.titleCharge-aware DRAM refresh reduction with value transformation-
dc.title.alternativeCharge-aware DRAM refresh reduction with value transformation-
dc.typeConference-
dc.type.rimsCONF-
dc.citation.beginningpage663-
dc.citation.endingpage676-
dc.citation.publicationname26th IEEE International Symposium on High Performance Computer Architecture, HPCA 2020-
dc.identifier.conferencecountryUS-
dc.identifier.conferencelocationSan Diego, CA-
dc.identifier.doi10.1109/HPCA47549.2020.00060-
dc.contributor.localauthorHuh, Jaehyuk-
dc.contributor.nonIdAuthorKwak, Wonsang-
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CS-Conference Papers(학술회의논문)
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