멀티 코어 시스템 및 멀티 코어 시스템의 작업 스케줄링 방법processor throttling 기법을 활용한 processor power-gating 구조 및 방법

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Assignee
KAIST
Country
CC (Cocos Islands)
Application Date
2014-05-29
Application Number
201410232954.5
Registration Date
2019-11-15
Registration Number
ZL201410232954.5
URI
http://hdl.handle.net/10203/273760
Appears in Collection
EE-Patent(특허)
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