The frequency multiplier with broadband frequency divide-by-2 followed by wide locking-range frequency tripler is presented in this article. The frequency divide-by-2 provides the quadrature signals with good mismatch performance across the entire operating frequency. The frequency tripler is quadrature locked while providing high fundamental tone rejection. The notch filtering with the source degeneration removes the harmonic tone due to the injected signal from the frequency divide-by-2 and minimizes the signal loss at the desired output frequency without additional current consumption. The proposed notch filter embedded within the injection-locked frequency tripler (ILFT) decouples the strict tradeoff between the selectivity (harmonic rejection) and the locking range, and thus enables the optimization of both parameters simultaneously. Quadrature outputs maintain good quadrature relations across the wide locking range based on the proposed layout and injection methods. The proposed circuit is fabricated in 45-nm CMOS technology. From the measurement result, the frequency multiplier achieves 25.61 dBc of harmonic rejection ratio without any additional bandpass filtering stages and exhibits the 57.6% of locking range corresponding to 20.4-36.6-GHz output frequency in the locked condition. The frequency multiplier with a multiplication ratio of 1.5 consumes 68 mA and occupies only 490 μ m x 560 μ m of chip-area operated from the 1.2 V of supply voltage.