Fast and Accurate Power Distribution Network Modeling of a Silicon Interposer for 2.5-D/3-D ICs With Multiarray TSVs

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dc.contributor.authorCho, Kyungjunko
dc.contributor.authorKim, Youngwooko
dc.contributor.authorKim, Subinko
dc.contributor.authorPark, Hyunwookko
dc.contributor.authorPark, Junyongko
dc.contributor.authorLee, Seongsooko
dc.contributor.authorShim, Daeyongko
dc.contributor.authorLee, Kangseolko
dc.contributor.authorOh, Sangmookko
dc.contributor.authorKim, Jounghoko
dc.date.accessioned2020-01-14T02:20:17Z-
dc.date.available2020-01-14T02:20:17Z-
dc.date.created2020-01-13-
dc.date.issued2019-09-
dc.identifier.citationIEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY, v.9, no.9, pp.1835 - 1846-
dc.identifier.issn2156-3950-
dc.identifier.urihttp://hdl.handle.net/10203/271152-
dc.description.abstractIn this paper, we first propose power distribution network (PDN) model of the perforated power and ground (P/G) planes including substrate effects and multiarray through-silicon vias (TSVs) for a silicon interposer. Since it is almost impossible to simulate a high metal density perforated PDN structure, we first suggest a modeling methodology for P/G perforated planes to reduce simulation time significantly with a high accuracy. To obtain the PDN impedance of a silicon interposer faster, we convert the perforated planes to solid planes with a dielectric mixture. The capacitance (C) and conductance (G) component of perforated P/G planes are precisely estimated based on the conformal mapping method. From the estimated C and G, the physical dimension and material properties of the dielectric mixture of solid P/G planes are determined, respectively. Because silicon interposer PDN consists of a periodic structure, we design and analyze the unit cell of a PDN thoroughly. From the unit cell analysis, the electrical characteristic of an entire PDN for a silicon interposer is successfully estimated. The PDN impedance of the proposed solid and perforated P/G planes and simulation time to obtain each PDN impedance are compared and evaluated, respectively. The proposed methodology is validated by a full 3-D electromagnetic (EM) simulation in the frequency range from 0.01 to 20 GHz. We also proposed models of multiarray P/G TSVs that can be applied to the various P/G patterns for a silicon interposer. From the inductance matrix considering current directions, the self- and mutual inductances of TSVs are accurately calculated. Because quasi-transverse electromagnetic mode is propagated through TSVs and the substrate dielectric of a silicon interposer can be regarded as a uniform dielectric, the capacitance and conductance of TSVs can be calculated from the inductance matrix. The proposed model of multiarray TSVs is also analyzed and verified by EM simulations in the frequency range from 0.01 to 20 GHz with a high accuracy.-
dc.languageEnglish-
dc.publisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC-
dc.titleFast and Accurate Power Distribution Network Modeling of a Silicon Interposer for 2.5-D/3-D ICs With Multiarray TSVs-
dc.typeArticle-
dc.identifier.wosid000504728300019-
dc.identifier.scopusid2-s2.0-85073801520-
dc.type.rimsART-
dc.citation.volume9-
dc.citation.issue9-
dc.citation.beginningpage1835-
dc.citation.endingpage1846-
dc.citation.publicationnameIEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY-
dc.identifier.doi10.1109/TCPMT.2019.2895083-
dc.contributor.localauthorKim, Joungho-
dc.contributor.nonIdAuthorShim, Daeyong-
dc.contributor.nonIdAuthorLee, Kangseol-
dc.contributor.nonIdAuthorOh, Sangmook-
dc.description.isOpenAccessN-
dc.type.journalArticleArticle-
dc.subject.keywordAuthorConformal mapping-
dc.subject.keywordAuthorhigh bandwidth memory (HBM)-
dc.subject.keywordAuthorpower distribution network (PDN)-
dc.subject.keywordAuthorsilicon interposer-
dc.subject.keywordAuthorthrough-silicon vias (TSVs)-
dc.subject.keywordPlusSIGNAL INTEGRITY DESIGN-
dc.subject.keywordPlusLINES-
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