Noise analysis of replica driving technique and its verification to 12-bit 200 MS/s pipelined ADC

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This study demonstrates the noise analysis of a replica driving MDAC architecture, which is verified by implementing a 12-bit 200 MS/s replica driving pipelined analogue-to-digital converter (ADC). Based on the noise design strategy with the target effective number of bits = 10.5-bit, the overall dynamic performance degradation by KT/C noise and thermal noise by an amplifier is alleviated by removing the front-end sample-and-hold (S/H) circuit, and the transconductance (g(m)) of the inner source follower is maximised by increasing the current and threshold voltage (V-T) reduction. Replica input sampling networks are designed for the first-stage sub-ADC and the first-stage MDAC with different aspect ratios to minimise the sampling skew for the S/H-less architecture. A prototype 12-bit 200 MS/s ADC is fabricated in a 65 nm complementary metal oxide semiconductor. The measured spurious-free dynamic range (SFDR) and signal-to-noise distortion ratio (SNDR) at a 1.0 MHz input signal is 82.6 and 65.6 dB, respectively, and SFDR and SNDR at the Nyquist (=99.0 MHz) input are 77.3 and 58.6 dB, respectively. The ADC core and the reference driver consume 53.9 and 13.2 mW, respectively, at a 1.2 V supply voltage.
Publisher
INST ENGINEERING TECHNOLOGY-IET
Issue Date
2019-11
Language
English
Article Type
Article
Citation

IET CIRCUITS DEVICES & SYSTEMS, v.13, no.8, pp.1277 - 1283

ISSN
1751-858X
DOI
10.1049/iet-cds.2018.5308
URI
http://hdl.handle.net/10203/270826
Appears in Collection
EE-Journal Papers(저널논문)
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