A Family of Stateful Memristor Gates for Complete Cascading Logic

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dc.contributor.authorKim, Kyung Minko
dc.contributor.authorWilliams, R. Stanleyko
dc.date.accessioned2019-12-13T01:27:33Z-
dc.date.available2019-12-13T01:27:33Z-
dc.date.created2019-12-02-
dc.date.created2019-12-02-
dc.date.created2019-12-02-
dc.date.created2019-12-02-
dc.date.issued2019-11-
dc.identifier.citationIEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, v.66, no.11, pp.4348 - 4355-
dc.identifier.issn1549-8328-
dc.identifier.urihttp://hdl.handle.net/10203/268838-
dc.description.abstractThe conditional switching of memristors to execute stateful implication logic is an example of in-memory computation to potentially provide high energy efficiency and improved computation speed by avoiding the movement of data back and forth between a processing chip and memory and/or storage. Since the first demonstration of memristor implication logic, a significant goal has been to improve the logic cascading to make it more practical. Here, we describe and experimentally demonstrate nine symmetry-related Boolean logic operations by controlling conventional Ta/TaOx/Pt memristors integrated in a crossbar array with applied voltage pulses to perform conditional SET or RESET switching involving two or three devices, i.e., a particular device is switched depending on the state of another device. We introduce a family of four stateful two-memristor logic gates along with the copy and negation operations that enable two-input-one-output complete logic. In addition, we reveal five stateful three-memristor gates that eliminate the need for a separate data copy operation, decreasing the number of steps required for a particular task. The diversity of gates made available by simply applying coordinated sequences of voltages to a memristor crossbar memory significantly improves stateful logic computing efficiency compared to similar approaches that have been proposed.-
dc.languageEnglish-
dc.publisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC-
dc.titleA Family of Stateful Memristor Gates for Complete Cascading Logic-
dc.typeArticle-
dc.identifier.wosid000494680200022-
dc.identifier.scopusid2-s2.0-85072586096-
dc.type.rimsART-
dc.citation.volume66-
dc.citation.issue11-
dc.citation.beginningpage4348-
dc.citation.endingpage4355-
dc.citation.publicationnameIEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS-
dc.identifier.doi10.1109/TCSI.2019.2926811-
dc.contributor.localauthorKim, Kyung Min-
dc.contributor.nonIdAuthorWilliams, R. Stanley-
dc.description.isOpenAccessY-
dc.type.journalArticleArticle-
dc.subject.keywordAuthorLogic circuits-
dc.subject.keywordAuthorLogic-in-memory-
dc.subject.keywordAuthormemristors-
dc.subject.keywordAuthorstateful logic-
dc.subject.keywordPlusOPERATIONS-
dc.subject.keywordPlusDESIGN-
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