30 Gb/s integrated receiver array for parallel optical interconnects

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A 30 Gb/s integrated receiver array for parallel optical interconnects with four channels have been designed and implemented in a 0.13 mu m CMOS technology. To achieve small area and low power consumption while maintaining large bandwidth and high gain, the integrated receiver has been implemented with a regulated cascode (RGC) transimpedance amplifier (TIA), resistive and capacitive degeneration and inductorless limiting amplifier (LA), which employs active feedback and negative capacitance. From the measurement results of the optical module using 850 nm photodiode (PD), the receiver showed a constant single-ended output swing of 320 mV up to 7.5 Gb/s/ch with clear eye diagrams and BER of <10(-12). With a voltage supply of 1.2 V, a figure of merit (FOM) of 8 mW/Gb/s was obtained with a small chip area per channel of 0.28 mm(2)/ch.
Publisher
INST ENGINEERING TECHNOLOGY-IET
Issue Date
2019-08
Language
English
Article Type
Article
Citation

JOURNAL OF ENGINEERING-JOE, no.8, pp.5375 - 5378

ISSN
2051-3305
DOI
10.1049/joe.2018.5260
URI
http://hdl.handle.net/10203/267404
Appears in Collection
EE-Journal Papers(저널논문)
Files in This Item
2019.08.29 J of Eng (Nga) 30 Gbps integrated receiver array for parallel optiical interconnects.pdf(2.34 MB)Download

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