Accurate wirelength prediction for placement driven synthesis through machine learning = 배치 기반 합성을 위한 기계학습을 이용한 정확한 배선길이 예측

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In sub-10nm technology, interconnect delay takes up an appreciable portion of circuit delay. Interconnect delay, however, cannot be accurately taken into account before placement and routing (P&R), which often causes many design iterations and increases turn around time. In this thesis, I propose a method of predicting wire length before P&R by using machine learning techniques. Effective parameters are identified and extracted from virtual P&R which is performed in conjunction with logic synthesis and then selected with linear discriminant analysis (LDA) to enhance the prediction accuracy. A model selection method is addressed in this thesis to filter some regression models that are not suitable for wirelength prediction. Multiple regression models are set up after training process, and the best model is chosen for each training sample during validation. After construction of models, we calculate the distance of each training sample to the nearby testing sample in parameter space, identify the training samples within a certain distance to the test sample, and the weight of each model is determined by the ratio of the best model in the identified samples. The final prediction is obtained by weighted sum of predictions in the models. The experiments demonstrate that the proposed method achieves on average of 15% smaller error rate compared to virtual P&R results.
Advisors
Shin, Young Sooresearcher신영수researcher
Description
한국과학기술원 :전기및전자공학부,
Publisher
한국과학기술원
Issue Date
2018
Identifier
325007
Language
eng
Description

학위논문(석사) - 한국과학기술원 : 전기및전자공학부, 2018.8,[iv, 41 p. :]

Keywords

Machine learning▼awirelength prediction▼aplacement driven synthesis▼aregression model combination; 기계 학습; 선길이 예측; 치 기반 합성을 위한; 귀; 델 조합

URI
http://hdl.handle.net/10203/266823
Link
http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=828586&flag=dissertation
Appears in Collection
EE-Theses_Master(석사논문)
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