Scheduling cluster tools for decreasing wafer throughput rate

Abstract

A cluster tool consists of several single-wafer processing chambers and a wafer-handling robot. There have been numerous works on cluster tool scheduling that determine the robot task sequence and timings. Most of them focus on increasing the wafer throughput rate. However, if we increase the throughput rate for cluster tools for non-bottleneck processes, we have excessive number of wafer lots waiting before the bottleneck, and hence excessive waiting times. Such excessive waiting times before taking the next process often also cause wafer quality degradation. Furthermore, if we control the lot release rate to meet the speed of the bottleneck stage, tools at non-bottleneck process stage may have excessive idle times. Such tool idle times cause changes or degradation of chambers’ atmosphere or states and hence increase quality risk. We therefore should decrease the throughput rate of the tools at the non-bottleneck process stages appropriately. However, if we decrease the wafer release rate into a tool to decrease the tool throughput rate, we have excessive waiting times of a wafer in a chamber after processing. Such wafer delays and their variability increase quality risk due to residual gases and heat. We therefore should develop a new scheduling method to decrease the throughput rate while not increasing wafer delays. In this thesis, we examine a new class of scheduling problems for single-armed cluster tools. We first examine how wafer delays for the conventional backward sequence, which is known to be optimal for single-armed tools, increase as the wafer delivery interval (WDI), that is, the reciprocal of the tool throughput rate, increases. We then propose a mixed integer programming model that determines a new robot task sequence that minimizes wafer delays while meeting the tool throughput rate upper bound. We also show a push-and-wait sequence reduce wafer delays, and provide a condition for which the sequence minimizes the wafer delays. We then propose a hybrid sequence that combines backward operations and push-and-wait operations appropriately. We show that such simple hybrid sequence effectively reduces wafer delays while meeting the throughput rate upper limit. We present experimental results for many different problem instances.