DC Field | Value | Language |
---|---|---|
dc.contributor.author | Park, Suneui | ko |
dc.contributor.author | Kim, Juyeop | ko |
dc.contributor.author | Hwang, Chanwoong | ko |
dc.contributor.author | Park, Hangi | ko |
dc.contributor.author | Yoo, Seyeon | ko |
dc.contributor.author | Seong, Taeho | ko |
dc.contributor.author | Choi, Jaehyouk | ko |
dc.date.accessioned | 2019-08-29T01:20:29Z | - |
dc.date.available | 2019-08-29T01:20:29Z | - |
dc.date.created | 2019-08-26 | - |
dc.date.created | 2019-08-26 | - |
dc.date.created | 2019-08-26 | - |
dc.date.created | 2019-08-26 | - |
dc.date.created | 2019-08-26 | - |
dc.date.created | 2019-08-26 | - |
dc.date.issued | 2019-08 | - |
dc.identifier.citation | IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS, v.29, no.8, pp.548 - 550 | - |
dc.identifier.issn | 1531-1309 | - |
dc.identifier.uri | http://hdl.handle.net/10203/266058 | - |
dc.description.abstract | This letter presents a delay-locked loop (DLL) that can have a wide harmonic-locking-free frequency range, by using a digital-to-analog converter-based (DAC-based) band-selection circuit (BSC). The proposed exponential DAC (EDAC) used for the BSC generates a set of initial control voltages that follow a geometric sequence while satisfying the condition for avoiding harmonic locking. Thus, the BSC can cover a much wider range of frequencies free from harmonic locking than it could cover when it used a conventional, linear DAC that generated a set of control voltages following an arithmetic sequence. In this letter, the DLL was fabricated in a 65-nm CMOS and it had a measured harmonic-locking-free range from 0.1 to 1.5 GHz. The measured 1-MHz phase noise and rms jitter at 1.0 GHz were -128 dBc/Hz and 1.99 ps, respectively. The active area was 0.052 mm(2), and the power consumption was 5.5 mW. | - |
dc.language | English | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.title | A 0.1-1.5-GHz Wide Harmonic-Locking-Free Delay-Locked Loop Using an Exponential DAC | - |
dc.type | Article | - |
dc.identifier.wosid | 000480357400014 | - |
dc.identifier.scopusid | 2-s2.0-85083639010 | - |
dc.type.rims | ART | - |
dc.citation.volume | 29 | - |
dc.citation.issue | 8 | - |
dc.citation.beginningpage | 548 | - |
dc.citation.endingpage | 550 | - |
dc.citation.publicationname | IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS | - |
dc.identifier.doi | 10.1109/LMWC.2019.2921718 | - |
dc.contributor.localauthor | Choi, Jaehyouk | - |
dc.contributor.nonIdAuthor | Park, Suneui | - |
dc.contributor.nonIdAuthor | Kim, Juyeop | - |
dc.contributor.nonIdAuthor | Hwang, Chanwoong | - |
dc.contributor.nonIdAuthor | Park, Hangi | - |
dc.contributor.nonIdAuthor | Yoo, Seyeon | - |
dc.contributor.nonIdAuthor | Seong, Taeho | - |
dc.description.isOpenAccess | N | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | Delay-locked loop (DLL) | - |
dc.subject.keywordAuthor | digital-to-analog converter (DAC) | - |
dc.subject.keywordAuthor | harmonic locking | - |
dc.subject.keywordPlus | DLL | - |
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