Receiver front-end architectures and designs for digital intensive radios

Abstract

This dissertation focuses on the circuit designs of the receiver front-end architectures with embedded filters, which are suitable to implement in digital-friendly advanced CMOS process. Three receivers are proposed for multi-mode multi-band (MMMB) and software-defined radio (SDR) applications. Firstly, a low-power interference-tolerance wideband receiver with post-LNA active N-path filter for RF channel selection is proposed for 802.1af/ah long-range Wi-Fi standards. By leveraging gain, noise, and filtering characteristics among the wideband LNA, high-Q active N-path filter, and reconfigurable analog baseband circuits, the proposed receiver achieves high gain, low noise, and high linearity with low power dissipation. The receiver provides narrow-bandwidth RF filtering with a small chip area. Implemented in a 40 nm CMOS process with the chip size of 1.1 mm x 2.25 mm, the full receiver shows a conversion gain of 84±1 dB and achieves NF from 3.4 to 3.9 dB in sub-GHz frequency bands. The measured in-band IIP3, out-of-band IIP3, and out-of-band IIP2 are -5.9, -0.5, and +62.5 dBm, respectively. The proposed receiver dissipates an average power of 41 mW. Secondly, this dissertation presents a low power discrete-time (DT) receiver supporting three broadcast services FM, T-DMB and DAB. The proposed output current passive mixer is merged with a switched-capacitor filter (SCF) in current mode for high linearity, low power and low complexity. The filter performs the second-order low-pass filtering with anti-aliasing ratio up to 70 dB at 1.6 MHz bandwidth. The chip is fabricated in a 90 nm CMOS technology and dissipates 11 mA current from 1.2 V supply. The receiver shows 48 dB maximum gain, 60 dB gain control range, 2.7 dB noise figure, and -22/0 dBm IIP3 in LNA high/low gain mode. Finally, a DT receiver for SDR applications is presented. The receiver chain includes a wideband LNA and high linearity current output passive mixers merged with SCFs to simplify analog circuitries and reduce power consumption. An RF transconductor with capacitive-peaking is proposed for the mixers to maximize the operating frequency. Implemented in a 0.18 μm CMOS process, the proposed receiver achieves a maximum voltage conversion gain of 41.2 dB, minimum NF of 3.8 dB, in-band IIP3 of -9 dBm, and out-of-band IIP3 of -6 dBm, respectively. The receiver operates from 0.7 to 2.4 GHz while dissipating 28-34 mA current from 1.8 V supplies.