Low-power high-performance artificial intelligence processor for autonomous mobile robots

Abstract

In recent years, autonomous mobile robots are receiving a lot of attention for many unmanned applications, such as package delivery and smart surveillance. In such applications, robots should be able to choose their own action to perform more challenging and complicated tasks in dynamically changing environments. However, the limited battery capacity makes it hard to implement intelligent decision making in robots because of the heavy computational costs. In this dissertation, we propose an artificial intelligence processor (AIP) to implement real-time path planning of autonomous mobile robots under low power consumption. In order to accelerate the path planning, the algorithm workload and the parallelization methods are analyzed first. While parallelizing the workload, the overhead caused by the duplicated computations between processors severely degraded the parallelization efficiency, so the partitioning of workload among the processors should be made without overlaps. The proposed AIP contains 4 tree search processors (TSPs) resulting in 32 threads in total, and a 3-level transposition table cache (TT$) is proposed to detect and avoid the duplicated computations as much as possible while minimizing the table lookup overhead. In addition, the workload for the path planning is reduced as the robot approaches the target position. Since the AIP does not need to be operated at the maximum operating frequency for all the time, the dynamic voltage and frequency scaling (DVFS) is adopted to minimize the power consumption without any performance loss. However, the conventional level shifter fails to translate the signals at low supply voltage and the timing constraints become more difficult to be met due to the large variation of MOSFETs. Therefore, a 10-transistor level shifter (10T-LS) and an on-chip PVT compensation circuit (PVTC) are proposed for stable and high-performance operation even at near-threshold voltage. As a result, the proposed $16 mm^2$ AIP is fabricated using 65 nm triple-well CMOS technology. It consumes only 1.1 mW at 0.55 V supply voltage and 7 MHz operating frequency and 151 mW at 1.2 V supply voltage and 245 MHz operating frequency. The AIP achieves fast search speed (470,000 search/s) and low energy consumption (79 nJ/search), and it is successfully applied to a battery-powered robot system for autonomous navigation without any collision in dynamic indoor environments.