(A) true background fully-integrated timing-skew calibration algorithm for time-interleaved ADCs

Abstract

In a similar concept to the parallel computing, time-interleaving scheme gave a birth to a new era of Analog-to-Digital converter (ADC) designs with high conversion rate and relaxed power-speed tradeoff. While favoring its innate ability to expand channels, its own artifacts such as the sampling timing-skews between channels have formed a barrier in adopting the time-interleaved architecture in general uses. In this thesis, a true background fully integrated timing-skew calibration scheme is discussed. By taking an advantage of pre-existent neighboring channel outputs, the derivative sign of the analog input is determined and is used to calibrate the sampling skews, without having to employ an additional input differentiating channel with a small sampling delay to note the directional change of the input. The proposed timing-skew calibration scheme is simple and occupies small silicon area while showing great robustness against noises, gain mismatches, and residual channel offsets.