Delta readout scheme for power-efficient CMOS image sensors

Abstract

In recent years, the emergence of high-performance CMOS image sensors (CISs) has been enlarging the imager market. The performance requirements of next-generation CISs have been increasing in terms of frame rate, power consumption, read noise, dynamic range, as well as pixel resolution. In particular, the pixel rate of most applications such as scientific imagers, sports activities, and industrial high speed machine vision sensors is getting faster as its pixel resolution and frame rate increase. Also, personalized mobile devices such as mobile phones and tablet PCs are equipped with CISs without exception, and even more CISs than one are requested for multiple functions. Given that all of these personalized devices are powered from batteries, a low-power design is essential for CISs.

In Chapter 1, a power-saving readout scheme for CMOS image sensors (CISs) that utilizes the image properties is presented. The proposed delta-readout ($\Delta$-readout) scheme reads the signal difference between two pixels located next to each other ($\Delta_{pixel}$) by utilizing the most significant bits (MSBs) information of the previous pixel. By effectively reducing the dynamic range of the signal, compensated by the $\Delta$-window checking, the proposed $\Delta$-readout scheme can reduce the effective number of decision cycles in a successive-approximation register (SAR) analog-to-digital converter (ADC) and reduce the power consumption while preserving the ADC performance. A prototype QQVGA CIS with ten 10-bit SAR ADCs in a multi-column-parallel (MCP) configuration was fabricated in a 0.18 $\mu$m 1P4M CIS process with a 4.4 $\mu$m pixel pitch. The measurement results of the implemented prototype CIS showed a maximum power-saving of 26% with a figure-of-merit (FoM) for ADC of 15 fJ/conversion-step.

In Chapter 2, a dual-imaging CIS that extracts a multi-level edge image in real time from conventional pixels for computer vision applications while a human-friendly normal image is also produced simultaneously utilizing a proposed speed/power-efficient dual-mode SAR ADC is presented. The dual-mode readout scheme operates in two modes, delta readout for fine-step conversion (FS mode) and single-slope readout for coarse-step conversion (CS mode), depending on the chosen pixel state for readout. If the chosen pixel is at a boundary of an object in the image, the ADC works in CS mode in order to readout the edge strength (ES), and ADC woks in FS mode if it is not. By displaying the ES, the edge image can be obtained in real time with no hardware/time overhead. A prototype QQVGA CIS with ten 10b SAR ADCs was fabricated in a 0.18 μm 1P4M CIS process with a 4.9 μm pixel pitch. Given its maximum pixel rate of 61.4 Mp/s, the prototype shows the-state-of-the-art FoMs: 70 pJ/pixel/frame, 0.35 $e^-$ ·nJ and 0.34 $e^-$·pJ/step.