Design of an asynchronous switch based on butterfly fat-tree for network-on-chip applications

Abstract

The future System-on-Chip (SoC) design will integrate a variety of intellectual properties (IPs). The clocked bus architectures to interconnect the IPs under the deep submicron technology suffer from problems related with the clock distribution, the synchronization of all IPs, the long arbitration delay and the limited bandwidth. These problems can be resolved by adopting new interconnection architecture such as Network-on-Chip (NoC) or the asynchronous design method. In this paper, a design methodology for an asynchronous switch based on butterfly fat-tree topology is proposed. The wormhole switching technique is adopted to reduce the latency and the buffer size. The source-based routing mechanism and the output buffering strategy are used to reduce the switch design cost and increase the performance.