An area efficient approach to design self-timed cryptosystems combatting DPA attack

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dc.contributor.authorLee, DWko
dc.contributor.authorHar, Dongsooko
dc.date.accessioned2019-04-15T16:32:01Z-
dc.date.available2019-04-15T16:32:01Z-
dc.date.created2013-05-08-
dc.date.issued2005-01-
dc.identifier.citationIEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, v.E88A, no.1, pp.331 - 333-
dc.identifier.issn0916-8508-
dc.identifier.urihttp://hdl.handle.net/10203/255887-
dc.description.abstractCryptosystems for smartcard are required to provide protection from Differential Power Analysis (DPA) attack. Self-timed circuit based cryptosystems demonstrate considerable resistance against DPA attack, but they take substantial circuit area. A novel approach offering up to 30% area reduction and maintaining DPA protection level close to DIMS scheme is proposed.-
dc.languageEnglish-
dc.publisherIEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG-
dc.subjectSECURITY-
dc.subjectCIRCUITS-
dc.titleAn area efficient approach to design self-timed cryptosystems combatting DPA attack-
dc.typeArticle-
dc.identifier.wosid000226443500044-
dc.identifier.scopusid2-s2.0-27544434498-
dc.type.rimsART-
dc.citation.volumeE88A-
dc.citation.issue1-
dc.citation.beginningpage331-
dc.citation.endingpage333-
dc.citation.publicationnameIEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES-
dc.identifier.doi10.1093/ietfec/E88-A.1.331-
dc.contributor.localauthorHar, Dongsoo-
dc.contributor.nonIdAuthorLee, DW-
dc.type.journalArticleLetter-
dc.subject.keywordAuthorDPA-
dc.subject.keywordAuthorself-timed circuit-
dc.subject.keywordAuthorDIMS-
dc.subject.keywordAuthorSTSC-
dc.subject.keywordPlusSECURITY-
dc.subject.keywordPlusCIRCUITS-
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