DC Field | Value | Language |
---|---|---|
dc.contributor.author | Oh, Dong-Ryeol | ko |
dc.contributor.author | 김종인 | ko |
dc.contributor.author | Jo, Dong-Shin | ko |
dc.contributor.author | Kim, Woo-Cheol | ko |
dc.contributor.author | Chang, Dong-Jin | ko |
dc.contributor.author | Ryu, Seung-Tak | ko |
dc.date.accessioned | 2019-03-19T01:06:11Z | - |
dc.date.available | 2019-03-19T01:06:11Z | - |
dc.date.created | 2019-02-18 | - |
dc.date.issued | 2019-01 | - |
dc.identifier.citation | IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.54, no.1, pp.288 - 297 | - |
dc.identifier.issn | 0018-9200 | - |
dc.identifier.uri | http://hdl.handle.net/10203/251517 | - |
dc.description.abstract | A 6-bit 2.5-GS/s 8x dynamic interpolating flash analog-to-digital converter (ADC) with an offset calibration technique for interpolated voltage-to-time converters (VTCs) is presented for high-speed applications. The dynamic-amplifier-structured VTC enables linear zero-crossing (ZX) interpolation in the time domain with an interpolation factor of 8, which reduces the number of front-end VTCs to one-sixth the original structure. The reduced number of VTCs lowers the power consumption, load capacitance to the track-and-holder (T/H), and overhead of VTC offset calibration. The sequential slope-matching offset calibration scheme is proposed not only for VTC offset but also for interpolated ZX accuracy. The prototype 6-bit 2.5-GS/s flash ADC was implemented in a 65-nm CMOS process and occupies a 0.12 mm(2) chip area, including offset calibration circuitry. The measured differential non-linearity (DNL) and integral non-linearity (INL) after offset calibration are 0.68 and 0.65 LSB, respectively. With a 1.23 GHz input, the measured signal-to-noise and distortion ratio (SNDR) and spurious-free dynamic range (SFDR) are 33.84 and 45.07 dB, respectively, with power consumption of 7.5 mW under a supply voltage of 0.85 V. The prototype ADC achieves a figure of merit (FoM) of 74.7 fJ/conversion step at 2.5 GS/s. | - |
dc.language | English | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.title | A 65-nm CMOS 6-bit 2.5-GS/s 7.5-mW 8x Time-Domain Interpolating Flash ADC With Sequential Slope-Matching Offset Calibration | - |
dc.type | Article | - |
dc.identifier.wosid | 000457637300026 | - |
dc.identifier.scopusid | 2-s2.0-85054495682 | - |
dc.type.rims | ART | - |
dc.citation.volume | 54 | - |
dc.citation.issue | 1 | - |
dc.citation.beginningpage | 288 | - |
dc.citation.endingpage | 297 | - |
dc.citation.publicationname | IEEE JOURNAL OF SOLID-STATE CIRCUITS | - |
dc.identifier.doi | 10.1109/JSSC.2018.2870554 | - |
dc.contributor.localauthor | Ryu, Seung-Tak | - |
dc.description.isOpenAccess | N | - |
dc.type.journalArticle | Article; Proceedings Paper | - |
dc.subject.keywordAuthor | Analog-to-digital conversion (ADC) | - |
dc.subject.keywordAuthor | cascaded phase interpolation (PI) | - |
dc.subject.keywordAuthor | flash ADC | - |
dc.subject.keywordAuthor | interpolation ADC | - |
dc.subject.keywordAuthor | offset calibration | - |
dc.subject.keywordAuthor | time-domain interpolation (TDI) | - |
dc.subject.keywordAuthor | voltage-to-time conversion (VTC) | - |
dc.subject.keywordPlus | SAR ADC | - |
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