Signal Integrity Design and Analysis of Differential High-Speed Serial Links in Silicon Interposer With Through-Silicon Via

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dc.contributor.authorCho, Kyungjunko
dc.contributor.authorKim, Youngwooko
dc.contributor.authorLee, Hyunsukko
dc.contributor.authorSong, Jinwookko
dc.contributor.authorPark, Junyongko
dc.contributor.authorLee, Seongsooko
dc.contributor.authorKim, Subinko
dc.contributor.authorPark, Gapyeolko
dc.contributor.authorSon, Kyungjuneko
dc.contributor.authorKim, Jounghoko
dc.date.accessioned2019-02-20T05:13:17Z-
dc.date.available2019-02-20T05:13:17Z-
dc.date.created2019-02-11-
dc.date.created2019-02-11-
dc.date.issued2019-01-
dc.identifier.citationIEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY, v.9, no.1, pp.107 - 121-
dc.identifier.issn2156-3950-
dc.identifier.urihttp://hdl.handle.net/10203/250376-
dc.description.abstractIn this paper, we, for the first time, designed and analyzed differential high-speed serial links of the silicon interposer including differential through-silicon-via (TSV) channels for a high-bandwidth memory (HBM) graphic module. The meshed ground plane and various parameters were considered in designing the silicon interposer. In addition, superior designs were proposed to improve signal integrity (SI) for the differential channels in the redistribution layer, TSVs, and the meshed ground. SI of the silicon interposer was successfully analyzed, and the corresponding results were verified based on a full 3-D electromagnetic solver and circuit simulations. A number of RLGC parameters were extracted and calculated, then adopted to verify the simulation results. The simulation results for the differential characteristic impedance and insertion loss were compared with those of the equivalent circuit. A mixed-mode conversion matrix was utilized to analyze differential-mode transmission. Moreover, a model for differential TSV channels was proposed to precisely analyze the electrical characteristics. The eye-diagram simulation was conducted to evaluate SI of the proposed designs in terms of an eye-opening voltage and timing jitter. The eye-opening voltage of the proposed design was 0.594 V, which is 45.69% of a peak-to-peak voltage of the assumed peripheral component interconnect (PCI)-express 4.0 interfaces. It is expected that the analysis and design methodologies of differential high-speed serial links for a silicon interposer could be widely adopted in the semiconductor industry.-
dc.languageEnglish-
dc.publisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC-
dc.titleSignal Integrity Design and Analysis of Differential High-Speed Serial Links in Silicon Interposer With Through-Silicon Via-
dc.typeArticle-
dc.identifier.wosid000456669500012-
dc.identifier.scopusid2-s2.0-85049139565-
dc.type.rimsART-
dc.citation.volume9-
dc.citation.issue1-
dc.citation.beginningpage107-
dc.citation.endingpage121-
dc.citation.publicationnameIEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY-
dc.identifier.doi10.1109/TCPMT.2018.2843442-
dc.contributor.localauthorKim, Joungho-
dc.description.isOpenAccessN-
dc.type.journalArticleArticle-
dc.subject.keywordAuthorDifferential channels-
dc.subject.keywordAuthorhigh-speed serial links-
dc.subject.keywordAuthormeshed ground plane-
dc.subject.keywordAuthorsilicon interposer-
dc.subject.keywordAuthorthrough-silicon via (TSV)-
dc.subject.keywordPlusTRANSMISSION-LINES-
dc.subject.keywordPlusMODEL-
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