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| NO | Title, Author(s) (Publication Title, Volume Issue, Page, Issue Date) |
|---|---|
| A Framework for Correction of Multi-Bit Soft Errors in L2 Caches Based on Redundancy Bhattacharya, Koustav; Ranganathan, Nagarajan; Kim, Soontae, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.17, pp.194 - 206, 2009-02 | |
| Write Buffer-Oriented Energy Reduction in the L1 Data Cache for Embedded Systems Lee, Jongmin; Kim, Soontae, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.24, no.3, pp.871 - 883, 2016-03 | |
| Fault buffers Enabling near-true voltage scaling in variation-sensitive L1 caches Mahmood, Tayyeb; Kim, Soontae, DESIGN AUTOMATION FOR EMBEDDED SYSTEMS, v.17, no.2, pp.411 - 438, 2013-06 |
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