Folded circuit synthesis: min-area logic synthesis using dual-edge-triggered flip-flops

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dc.contributor.authorHan, Inhakko
dc.contributor.authorShin, Youngsooko
dc.date.accessioned2018-12-20T06:52:51Z-
dc.date.available2018-12-20T06:52:51Z-
dc.date.created2018-11-30-
dc.date.created2018-11-30-
dc.date.issued2018-08-
dc.identifier.citationACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS, v.23, no.5, pp.61:1 - 61:21-
dc.identifier.issn1084-4309-
dc.identifier.urihttp://hdl.handle.net/10203/248316-
dc.description.abstractThe area required by combinational logic of a sequential circuit based on standard flip-flops can be reduced by identifying subcircuits that are identical. Pairs of matching subcircuits can then be replaced by circuits in which dual-edge-triggered flip-flops operate on multiplexed data at the rising and falling edges of the clock signal. We show how to modify the Boolean network describing a combinational logic to increase the opportunities for folding, without affecting its function. Experiments with benchmark circuits achieved an average reduction in circuit area of 18%.-
dc.languageEnglish-
dc.publisherASSOC COMPUTING MACHINERY-
dc.titleFolded circuit synthesis: min-area logic synthesis using dual-edge-triggered flip-flops-
dc.typeArticle-
dc.identifier.wosid000457132900006-
dc.identifier.scopusid2-s2.0-85052604109-
dc.type.rimsART-
dc.citation.volume23-
dc.citation.issue5-
dc.citation.beginningpage61:1-
dc.citation.endingpage61:21-
dc.citation.publicationnameACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS-
dc.identifier.doi10.1145/3229082-
dc.contributor.localauthorShin, Youngsoo-
dc.description.isOpenAccessN-
dc.type.journalArticleArticle-
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EE-Journal Papers(저널논문)
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