DC Field | Value | Language |
---|---|---|
dc.contributor.author | Han, Inhak | ko |
dc.contributor.author | Shin, Youngsoo | ko |
dc.date.accessioned | 2018-12-20T06:52:51Z | - |
dc.date.available | 2018-12-20T06:52:51Z | - |
dc.date.created | 2018-11-30 | - |
dc.date.created | 2018-11-30 | - |
dc.date.issued | 2018-08 | - |
dc.identifier.citation | ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS, v.23, no.5, pp.61:1 - 61:21 | - |
dc.identifier.issn | 1084-4309 | - |
dc.identifier.uri | http://hdl.handle.net/10203/248316 | - |
dc.description.abstract | The area required by combinational logic of a sequential circuit based on standard flip-flops can be reduced by identifying subcircuits that are identical. Pairs of matching subcircuits can then be replaced by circuits in which dual-edge-triggered flip-flops operate on multiplexed data at the rising and falling edges of the clock signal. We show how to modify the Boolean network describing a combinational logic to increase the opportunities for folding, without affecting its function. Experiments with benchmark circuits achieved an average reduction in circuit area of 18%. | - |
dc.language | English | - |
dc.publisher | ASSOC COMPUTING MACHINERY | - |
dc.title | Folded circuit synthesis: min-area logic synthesis using dual-edge-triggered flip-flops | - |
dc.type | Article | - |
dc.identifier.wosid | 000457132900006 | - |
dc.identifier.scopusid | 2-s2.0-85052604109 | - |
dc.type.rims | ART | - |
dc.citation.volume | 23 | - |
dc.citation.issue | 5 | - |
dc.citation.beginningpage | 61:1 | - |
dc.citation.endingpage | 61:21 | - |
dc.citation.publicationname | ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS | - |
dc.identifier.doi | 10.1145/3229082 | - |
dc.contributor.localauthor | Shin, Youngsoo | - |
dc.description.isOpenAccess | N | - |
dc.type.journalArticle | Article | - |
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