Hybrid Sorting Architecture for Low-latency Successive Cancellation List Decoding of Polar Codes

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This paper presents a new sorting architecture for low-latency successive cancellation list decoding (SCLD) of polar codes. By investigating the dataflow of SCLD, it is discovered that the metric sorting and the metric computation, which have been performed in a serial manner, can be parallelized if the metric sorter is decomposable into two subcomponents. To exploit such a property, a low-complexity sorting architecture adequate for the decomposition is developed by hybridizing bitonic and odd-even sorts. The proposed architecture not only diminishes the latency of SCLD significantly, but also attains the hardware complexity as low as that of the state-of-the-art work.
Publisher
IEEK PUBLICATION CENTER
Issue Date
2018-10
Language
English
Article Type
Article
Citation

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, v.18, no.5, pp.593 - 601

ISSN
1598-1657
DOI
10.5573/JSTS.2018.18.5.593
URI
http://hdl.handle.net/10203/246697
Appears in Collection
EE-Journal Papers(저널논문)
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