A Comprehensive Study of a Single-Transistor Latch in Vertical Pillar-Type FETs With Asymmetric Source and Drain

Abstract

The single-transistor latch in vertical pillartype FETs with asymmetric source and drain (S/D) was investigated for capacitorless one transistor dynamic random access memory (1T-DRAM). The asymmetric S/D is produced by the different energies of ion implantation at different depths of the pillar. The window of latch voltage (Delta(VL)), which is the difference between the latch-up voltage (Delta V-LU) and latch-down voltage (V-LD ), was dominantly governed by VLD. Fluctuation in the A Delta V-L(= V-LU-V-LD) is mainly induced by different series resistances (R-SD). The variation in R-SD becomes increasingly fatal to the stable operation of a 1T-DRAM with a smaller diameter; therefore, uniform control of R-SD is very important for the read operation in 1T-DRAM. In addition, the doping concentration of the source should be high for wide Delta V-L.