A 3.2-GHz Supply Noise-Insensitive PLL Using a Gate-Voltage-Boosted Source-Follower Regulator and Residual Noise Cancellation

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In this brief, we propose a supply noise-insensitive charge-pump phase-locked loop (PLL) using a source-follower (SF) regulator and noise cancellation. In order to minimize the voltage drop of the SF regulator while improving supply rejection, a gate-voltage-boosting technique and the body-controlled noise cancellation are proposed. To suppress the phase noise from the ring oscillator, a reference multiplier is employed to maximize the PLL loop bandwidth. Implemented in 65-nm CMOS, a prototype PLL at 3.2 GHz achieves supply noise spur of less than -33 dBc for a 50-mV(pp) supply noise around the loop bandwidth while consuming 3.12 mW from a 1-V supply.
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Issue Date
2018-10
Language
English
Article Type
Article
Keywords

PHASE-LOCKED LOOPS; RING OSCILLATORS

Citation

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.26, no.10, pp.2170 - 2174

ISSN
1063-8210
DOI
10.1109/TVLSI.2018.2845859
URI
http://hdl.handle.net/10203/246331
Appears in Collection
EE-Journal Papers(저널논문)
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