3x-oversampling based clock and data recovery in high speed memory interface = 고속 메모리 인터페이스에서의 3배 추가 표본을 이용한 클럭-데이터 복원

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With the rapid growth of data center’s IP traffic, there is a growing demand for a higher speed and larger capacity memory in the server-oriented memory. A load reduced dual in-line memory module (LRDIMM), including data buffers (DBs), was selected as a new standard for memory controller to drive much more memory at higher speed in a memory channel. The proposed DB compensates for signal integrity that is corrupted by crosstalk noise from adjacent channels that is becoming dominant performance limiting source as the data rate gets faster. 3x-oversampling based Clock and Data Recovery (CDR) circuit is implemented including Instantaneous Multiple Phase Generators (IMPG) to obtain 3 samples within 1 unit interval. Phase drift calibration scheme is also implemented for continuous tracking of the internal phase change even in a random access environment. The proposed data buffer is implemented using 40nm process. The operating speed supports 3.2Gbps, the maximum rate defined by the DDR4 DB standard, and the proposed structure get a signal-to-noise ratio (SNR) improvement of 1.5 dB at BER of $10^-5}.
Advisors
Bae, Hyeon-Minresearcher배현민researcher
Description
한국과학기술원 :전기및전자공학부,
Publisher
한국과학기술원
Issue Date
2017
Identifier
325007
Language
eng
Description

학위논문(석사) - 한국과학기술원 : 전기및전자공학부, 2017.2,[iii, 28 p. :]

Keywords

high speed memory interface; crosstalk; oversampling; CDR; instantaneous multi-phase generation; 고속 메모리 인터페이스; 누화; 추가 표본; 클럭-데이터 복원; 순간 다수 위상 발생기

URI
http://hdl.handle.net/10203/243320
Link
http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=675428&flag=dissertation
Appears in Collection
EE-Theses_Master(석사논문)
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