3x-oversampling based clock and data recovery in high speed memory interface

Abstract

With the rapid growth of data center’s IP traffic, there is a growing demand for a higher speed and larger capacity memory in the server-oriented memory. A load reduced dual in-line memory module (LRDIMM), including data buffers (DBs), was selected as a new standard for memory controller to drive much more memory at higher speed in a memory channel. The proposed DB compensates for signal integrity that is corrupted by crosstalk noise from adjacent channels that is becoming dominant performance limiting source as the data rate gets faster. 3x-oversampling based Clock and Data Recovery (CDR) circuit is implemented including Instantaneous Multiple Phase Generators (IMPG) to obtain 3 samples within 1 unit interval. Phase drift calibration scheme is also implemented for continuous tracking of the internal phase change even in a random access environment. The proposed data buffer is implemented using 40nm process. The operating speed supports 3.2Gbps, the maximum rate defined by the DDR4 DB standard, and the proposed structure get a signal-to-noise ratio (SNR) improvement of 1.5 dB at BER of $10^-5}.